{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/10452551","patent":{"patent_number":"10452551","title":"PROGRAMMABLE MEMORY PREFETCHER FOR PREFETCHING MULTIPLE CACHE LINES BASED ON DATA IN A PREFETCH ENGINE CONTROL REGISTER","assignee":"Unknown","inventors":["Ganesh Venkatesh","Christopher B. Wilkerson","Seth H. Pugsley","Deborah T. Marr"],"filing_date":null,"publication_date":"2019-10-22T00:00:00.000Z","cpc_codes":[],"num_claims":null,"abstract":null},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"PROGRAMMABLE MEMORY PREFETCHER FOR PREFETCHING MULTIPLE CACHE LINES BASED ON DATA IN A PREFETCH ENGINE CONTROL REGISTER","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/10452551","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/10452551","citation_suggestion":"Patentable. \"PROGRAMMABLE MEMORY PREFETCHER FOR PREFETCHING MULTIPLE CACHE LINES BASED ON DATA IN A PREFETCH ENGINE CONTROL REGISTER\" (10452551). https://patentable.app/patents/10452551","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/10452551","json":"https://patentable.app/api/llm-context/10452551","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T17:35:59.127Z"}