{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/10474774","patent":{"patent_number":"10474774","title":"POWER AND PERFORMANCE SORTING OF MICROPROCESSORS FROM FIRST INTERCONNECT LAYER TO WAFER FINAL TEST","assignee":"Unknown","inventors":["Emrah Acar","Moyra K. McManus","Sani R. Nassif","Matthew J. Sullivan"],"filing_date":null,"publication_date":"2019-11-12T00:00:00.000Z","cpc_codes":[],"num_claims":null,"abstract":null},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"POWER AND PERFORMANCE SORTING OF MICROPROCESSORS FROM FIRST INTERCONNECT LAYER TO WAFER FINAL TEST","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/10474774","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/10474774","citation_suggestion":"Patentable. \"POWER AND PERFORMANCE SORTING OF MICROPROCESSORS FROM FIRST INTERCONNECT LAYER TO WAFER FINAL TEST\" (10474774). https://patentable.app/patents/10474774","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/10474774","json":"https://patentable.app/api/llm-context/10474774","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T03:36:20.878Z"}