{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/10552316","patent":{"patent_number":"10552316","title":"CONTROLLING NAND OPERATION LATENCY","assignee":"Unknown","inventors":["Giuseppe D'Eliseo","Luigi Esposito","Xinghui Duan","Lucia Santojanni","Massimo Iaculo"],"filing_date":null,"publication_date":"2020-02-04T00:00:00.000Z","cpc_codes":[],"num_claims":null,"abstract":null},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"CONTROLLING NAND OPERATION LATENCY","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/10552316","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/10552316","citation_suggestion":"Patentable. \"CONTROLLING NAND OPERATION LATENCY\" (10552316). https://patentable.app/patents/10552316","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/10552316","json":"https://patentable.app/api/llm-context/10552316","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T21:20:49.434Z"}