{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10474370","patent":{"patent_number":"US-10474370","title":"Method and system for mitigating the effect of write and read disturbances in solid state memory regions","assignee":null,"inventors":[],"filing_date":"2016-06-28T00:00:00.000Z","publication_date":"2019-11-12T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F"],"num_claims":20,"abstract":"A method for mitigating the effect of write disturbances in solid state memory. The method includes receiving a request to write to a memory location of the solid state memory, writing to the memory location, identifying a disturbed memory location, identifying a memory region that includes the disturbed memory location, identifying an address, in the memory region, of the disturbed memory location, generating an address hash from the address, and making a first determination that a history of disturbed memory locations in the memory region includes the address hash. The method further includes, based on the first determination, clearing the history of disturbed memory locations, making a second determination that a wear level operation is due, and based on the second determination, performing the wear level operation."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method and system for mitigating the effect of write and read disturbances in solid state memory regions","description":"A method for mitigating the effect of write disturbances in solid state memory. The method includes receiving a request to write to a memory location of the solid state memory, writing to the memory l","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10474370","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10474370","citation_suggestion":"Patentable. \"Method and system for mitigating the effect of write and read disturbances in solid state memory regions\" (US-10474370). https://patentable.app/patents/US-10474370","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10474370","json":"https://patentable.app/api/llm-context/US-10474370","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T00:38:30.890Z"}