{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10474390","patent":{"patent_number":"US-10474390","title":"Systems and method for buffering data using a delayed write data signal and a memory receiving write addresses in a first order and read addresses in a second order","assignee":null,"inventors":[],"filing_date":"2017-05-04T00:00:00.000Z","publication_date":"2019-11-12T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G11C","G11C"],"num_claims":20,"abstract":"A circuit includes a memory and an address generator configured to generate a write address signal and a read address signal, where the write address signal has a first delay relative to the read address signal. The memory is configured to receive a first plurality of write addresses, from the write address signal, including a first plurality of addresses of the memory in a first order, and write, to the first plurality of write addresses, a first plurality of data words during a first time period. The memory is further configured to receive a first plurality of read addresses, from the read address signal, including the first plurality of addresses in a second order, and read, from the first plurality of read addresses, the first plurality of data words during a second time period. The first and second time periods partially overlap. The first order may be one of a natural order and a modified order, with the second order being the other of the natural order and the modified order, and the modified order may be one of a bit-reversed order and a digit-reversed order. The memory may have different write modes, and may be a read-before-write memory or a write-before-read memory."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Systems and method for buffering data using a delayed write data signal and a memory receiving write addresses in a first order and read addresses in a second order","description":"A circuit includes a memory and an address generator configured to generate a write address signal and a read address signal, where the write address signal has a first delay relative to the read addr","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10474390","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10474390","citation_suggestion":"Patentable. \"Systems and method for buffering data using a delayed write data signal and a memory receiving write addresses in a first order and read addresses in a second order\" (US-10474390). https://patentable.app/patents/US-10474390","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10474390","json":"https://patentable.app/api/llm-context/US-10474390","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T15:32:57.198Z"}