{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10475504","patent":{"patent_number":"US-10475504","title":"Integrated protecting circuit of semiconductor device","assignee":null,"inventors":[],"filing_date":"2016-10-26T00:00:00.000Z","publication_date":"2019-11-12T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C"],"num_claims":20,"abstract":"Disclosed is an integrated protecting circuit, which detects ESD and EOS pulses to prevent an over-voltage from being applied to a semiconductor device. The integrated protecting circuit includes a first detector configured to detect an occurrence of an electrical over-stress between a first node to which a first voltage is applied and a second node to which a second voltage is applied, a second detector configured to detect an occurrence of an electrostatic discharge between the first and second nodes, a determination circuit configured to receive separate outputs of the first and second detectors at the same time and to generate a control signal, and a clamping device configured to perform a turn on/off operation in response to the control signal such that a voltage between the first and second nodes is clamped into a constant voltage."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Integrated protecting circuit of semiconductor device","description":"Disclosed is an integrated protecting circuit, which detects ESD and EOS pulses to prevent an over-voltage from being applied to a semiconductor device. The integrated protecting circuit includes a fi","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10475504","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10475504","citation_suggestion":"Patentable. \"Integrated protecting circuit of semiconductor device\" (US-10475504). https://patentable.app/patents/US-10475504","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10475504","json":"https://patentable.app/api/llm-context/US-10475504","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T20:05:38.959Z"}