{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10475511","patent":{"patent_number":"US-10475511","title":"Read operation with data latch and signal termination for 1TNR memory array","assignee":null,"inventors":[],"filing_date":"2018-11-16T00:00:00.000Z","publication_date":"2019-11-12T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":9,"abstract":"Two-terminal memory can be formed into a memory array that contains many discrete memory cells in a physical and a logical arrangement. Where each memory cell is isolated from surrounding circuitry by a single transistor, the resulting array is referred to as a 1T1R memory array. In contrast, where a group of memory cells are isolated from surrounding circuitry by a single transistor, the result is a 1TnR memory array. Because memory cells of a group are not isolated among themselves in the 1TnR case, bit disturb effects are theoretically possible when operating on a single memory cell. Read operations are disclosed for two-terminal memory devices configured to mitigate bit disturb effects, despite a lack of isolation transistors among memory cells of an array. Disclosed operations can facilitate reduced bit disturb effects even for high density two-terminal memory cell arrays."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Read operation with data latch and signal termination for 1TNR memory array","description":"Two-terminal memory can be formed into a memory array that contains many discrete memory cells in a physical and a logical arrangement. Where each memory cell is isolated from surrounding circuitry by","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10475511","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10475511","citation_suggestion":"Patentable. \"Read operation with data latch and signal termination for 1TNR memory array\" (US-10475511). https://patentable.app/patents/US-10475511","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10475511","json":"https://patentable.app/api/llm-context/US-10475511","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T21:23:34.639Z"}