{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10475923","patent":{"patent_number":"US-10475923","title":"Method and structure for forming vertical transistors with various gate lengths","assignee":null,"inventors":[],"filing_date":"2018-06-14T00:00:00.000Z","publication_date":"2019-11-12T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":12,"abstract":"Various methods and structures for fabricating a plurality of vertical fin FETs on the same semiconductor substrate in which a first gate length of a first gate in a first vertical fin FET is less than a second gate length of a second gate in a second vertical fin FET. A difference in gate lengths between different vertical fin FETs can be precisely fabricated by using atomic layer silicon germanium epitaxy. Gate length offset is formed at a bottom source/drain junction region of each vertical fin FET transistor, which allows downstream processing for all vertical fin FET transistors to be the same."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method and structure for forming vertical transistors with various gate lengths","description":"Various methods and structures for fabricating a plurality of vertical fin FETs on the same semiconductor substrate in which a first gate length of a first gate in a first vertical fin FET is less tha","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10475923","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10475923","citation_suggestion":"Patentable. \"Method and structure for forming vertical transistors with various gate lengths\" (US-10475923). https://patentable.app/patents/US-10475923","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10475923","json":"https://patentable.app/api/llm-context/US-10475923","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T00:36:04.758Z"}