{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10476659","patent":{"patent_number":"US-10476659","title":"SPDIF clock and data recovery with sample rate converter","assignee":null,"inventors":[],"filing_date":"2018-07-30T00:00:00.000Z","publication_date":"2019-11-12T00:00:00.000Z","cpc_codes":["H04L","G06F","H04L","H04L"],"num_claims":20,"abstract":"A system can include a digital oversampler configured to oversample an input data stream; a rate generator configured to select a frequency that is not less than an expected frequency of the input data stream; a rate generator clock of the rate generator configured to output a clock signal that has the selected frequency; a sample receiver configured to receive at least one sample of the input data stream from the digital oversampler; a sample counter configured to be incremented by each received sample responsive to a determination that the sample receiver has received at least one sample of the input data stream from the digital oversampler; a sample rate converter configured to accumulate samples from the sample receiver at the rate of a “toothless” clock signal, wherein the sample counter is configured to be decremented by the “toothless” clock signal at the selected frequency responsive to a determination that the sample receiver has not received at least one sample of the input data stream from the digital oversampler; and an AND gate configured to pass the “toothless” clock signal to the sample rate converter responsive to a determination that an output of the sample counter is greater than zero."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"SPDIF clock and data recovery with sample rate converter","description":"A system can include a digital oversampler configured to oversample an input data stream; a rate generator configured to select a frequency that is not less than an expected frequency of the input dat","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10476659","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10476659","citation_suggestion":"Patentable. \"SPDIF clock and data recovery with sample rate converter\" (US-10476659). https://patentable.app/patents/US-10476659","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10476659","json":"https://patentable.app/api/llm-context/US-10476659","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T04:00:54.791Z"}