{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10481819","patent":{"patent_number":"US-10481819","title":"Memory devices with multiple sets of latencies and methods for operating the same","assignee":null,"inventors":[],"filing_date":"2017-10-30T00:00:00.000Z","publication_date":"2019-11-19T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G11C","G11C","G11C","G11C"],"num_claims":22,"abstract":"Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several sets of latencies (e.g., read, write, or write recovery latencies), and the memory device or system may apply a set of latencies depending on which features of the memory device are enabled. For example, control circuitry may be configured to enable one or more features during operations on a memory array, and the control circuitry may apply a set of latency values based on a number or type of features that are enabled. The sets of latency values may depend, for example, on whether various control features (e.g., dynamic voltage frequency scaling) are enabled, and a device may operate within certain frequency ranges irrespective of other characteristics (e.g., mode register values) or latencies applied."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory devices with multiple sets of latencies and methods for operating the same","description":"Methods, systems, and apparatuses related to memory operation with multiple sets of latencies are disclosed. A memory device or system that includes a memory device may be operable with one or several","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10481819","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10481819","citation_suggestion":"Patentable. \"Memory devices with multiple sets of latencies and methods for operating the same\" (US-10481819). https://patentable.app/patents/US-10481819","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10481819","json":"https://patentable.app/api/llm-context/US-10481819","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T00:37:55.274Z"}