{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10482023","patent":{"patent_number":"US-10482023","title":"I/O path optimization based on cache slot location","assignee":null,"inventors":[],"filing_date":"2016-09-29T00:00:00.000Z","publication_date":"2019-11-19T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F","H04L","H04L","G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F"],"num_claims":21,"abstract":"Processing an I/O operation may include the host selecting one of the available paths over which to send each I/O operation to the data storage system. The selected path may be to a particular director that has responsibility for cache slot allocation and locally accessing the cache slot predicted to include the data of the I/O operation. The host may understand the cache slot allocation algorithm used on the data storage system and how cache slots are allocated for particular logical devices and tracks or locations on the logical devices. The host may direct I/Os down a path to a particular director that has, or will allocate, the cache slot used for the I/Os. There may be multiple directors in a data storage system including a distributed global memory. Each director may locally access a group of cache slots and communicate over a fabric to access the distributed global memory."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"I/O path optimization based on cache slot location","description":"Processing an I/O operation may include the host selecting one of the available paths over which to send each I/O operation to the data storage system. The selected path may be to a particular directo","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10482023","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10482023","citation_suggestion":"Patentable. \"I/O path optimization based on cache slot location\" (US-10482023). https://patentable.app/patents/US-10482023","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10482023","json":"https://patentable.app/api/llm-context/US-10482023","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T21:22:07.833Z"}