{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10482938","patent":{"patent_number":"US-10482938","title":"Word-line timing control in a semiconductor memory device and a memory system including the same","assignee":null,"inventors":[],"filing_date":"2017-08-31T00:00:00.000Z","publication_date":"2019-11-19T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C"],"num_claims":18,"abstract":"A semiconductor memory device and method of operation that is capable of reducing disturbance of adjacent word lines. A memory cell array includes a plurality of memory cells coupled to a plurality of word-lines and a plurality of bit-lines. A first word-line, which is selected in response to an access address received from the memory controller, is enabled in response to a first command received from a memory controller, and the first word-line is disabled internally in the semiconductor memory device or in response to a disable command received from the memory controller after a reference time interval elapses. The reference time interval starts from a first time point when the first command is applied to the semiconductor memory device, and corresponds to a time interval equal to or greater than a row active time interval of the semiconductor memory device."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Word-line timing control in a semiconductor memory device and a memory system including the same","description":"A semiconductor memory device and method of operation that is capable of reducing disturbance of adjacent word lines. A memory cell array includes a plurality of memory cells coupled to a plurality of","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10482938","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10482938","citation_suggestion":"Patentable. \"Word-line timing control in a semiconductor memory device and a memory system including the same\" (US-10482938). https://patentable.app/patents/US-10482938","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10482938","json":"https://patentable.app/api/llm-context/US-10482938","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T17:09:23.336Z"}