{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10482978","patent":{"patent_number":"US-10482978","title":"Read voltage optimization method, memory storage device and memory control circuit unit","assignee":null,"inventors":[],"filing_date":"2018-07-30T00:00:00.000Z","publication_date":"2019-11-19T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C"],"num_claims":26,"abstract":"A decoding method is provided. The method includes selecting a target word line among a plurality of word lines; respectively reading a plurality of target memory cells of the target word-line by using different X read voltage sets to obtain corresponding X Gray code summation sets; calculating a Gray code count summation difference of the Gray code count summations at the same sequence position respectively in N−1 Gray code count summations between every pair of adjacent Gray code summation sets of the X Gray code summation sets, so as to obtain X−1 Gray code count summation difference sets corresponding to all pairs of the Gray code summation sets; and deciding N−1 optimized read voltages from X*(N−1) read voltages belonging to the X read voltage sets according to the X−1 Gray code count summation difference sets."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Read voltage optimization method, memory storage device and memory control circuit unit","description":"A decoding method is provided. The method includes selecting a target word line among a plurality of word lines; respectively reading a plurality of target memory cells of the target word-line by usin","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10482978","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10482978","citation_suggestion":"Patentable. \"Read voltage optimization method, memory storage device and memory control circuit unit\" (US-10482978). https://patentable.app/patents/US-10482978","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10482978","json":"https://patentable.app/api/llm-context/US-10482978","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T18:24:24.663Z"}