{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10482981","patent":{"patent_number":"US-10482981","title":"Preventing refresh of voltages of dummy memory cells to reduce threshold voltage downshift for select gate transistors","assignee":null,"inventors":[],"filing_date":"2018-02-20T00:00:00.000Z","publication_date":"2019-11-19T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":22,"abstract":"Apparatuses and techniques are described for reducing charge loss in a select gate transistor in a memory device. In one aspect, a refresh operation is performed repeatedly to couple up data word line voltages but not dummy word line voltages. The refresh operation can involve applying a voltage pulse to the data word lines of a block when the block is not being used for a storage operation such as a program, read or erase operation. When the voltage pulse is applied to the data word lines, the dummy word lines can be set to a low level such as 0 V. This low level prevents or limits coupling up of the dummy memory cells to avoid creating an electric field which can cause holes to move from the dummy memory cells to adjacent select gate transistors."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Preventing refresh of voltages of dummy memory cells to reduce threshold voltage downshift for select gate transistors","description":"Apparatuses and techniques are described for reducing charge loss in a select gate transistor in a memory device. In one aspect, a refresh operation is performed repeatedly to couple up data word line","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10482981","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10482981","citation_suggestion":"Patentable. \"Preventing refresh of voltages of dummy memory cells to reduce threshold voltage downshift for select gate transistors\" (US-10482981). https://patentable.app/patents/US-10482981","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10482981","json":"https://patentable.app/api/llm-context/US-10482981","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T18:53:55.351Z"}