{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10483232","patent":{"patent_number":"US-10483232","title":"Method for fabricating bump structures on chips with panel type process","assignee":null,"inventors":[],"filing_date":"2017-08-23T00:00:00.000Z","publication_date":"2019-11-19T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":12,"abstract":"A method for fabricating bump structures on chips with a panel type process is provided. First, a panel type substrate is provided. Semiconductor chips are fixed on the panel type substrate. Each semiconductor chip includes metal pads and a passivation layer exposing the metal pads. At least an electroless plating process is performed to form under bump metallurgy structures on the metal pads. The method simplifies the processes of forming electrical connections for semiconductor chips. The panel type process can effectively increase the yield, and reduce the manufacturing cost."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method for fabricating bump structures on chips with panel type process","description":"A method for fabricating bump structures on chips with a panel type process is provided. First, a panel type substrate is provided. Semiconductor chips are fixed on the panel type substrate. Each semi","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10483232","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10483232","citation_suggestion":"Patentable. \"Method for fabricating bump structures on chips with panel type process\" (US-10483232). https://patentable.app/patents/US-10483232","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10483232","json":"https://patentable.app/api/llm-context/US-10483232","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T09:17:23.028Z"}