{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10483379","patent":{"patent_number":"US-10483379","title":"High resistivity silicon-on-insulator wafer manufacturing method for reducing substrate loss","assignee":null,"inventors":[],"filing_date":"2018-01-11T00:00:00.000Z","publication_date":"2019-11-19T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":24,"abstract":"A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum bulk region resistivity of at least about 500 ohm-cm; a semiconductor nitride layer in contact with the semiconductor handle substrate, the semiconductor nitride layer selected from the group consisting of aluminum nitride, boron nitride, indium nitride, gallium nitride, aluminum gallium nitride, aluminum gallium indium nitride, aluminum gallium indium boron nitride, and combinations thereof; a dielectric layer in contact with the semiconductor nitride layer; and a semiconductor device layer in contact with the dielectric layer."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"High resistivity silicon-on-insulator wafer manufacturing method for reducing substrate loss","description":"A multilayer composite structure and a method of preparing a multilayer composite structure are provided. The multilayer composite structure comprises a semiconductor handle substrate having a minimum","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10483379","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10483379","citation_suggestion":"Patentable. \"High resistivity silicon-on-insulator wafer manufacturing method for reducing substrate loss\" (US-10483379). https://patentable.app/patents/US-10483379","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10483379","json":"https://patentable.app/api/llm-context/US-10483379","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T17:38:49.259Z"}