{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10488460","patent":{"patent_number":"US-10488460","title":"Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator","assignee":null,"inventors":[],"filing_date":"2016-02-11T00:00:00.000Z","publication_date":"2019-11-26T00:00:00.000Z","cpc_codes":["G06F"],"num_claims":26,"abstract":"A method, system and computer program product are disclosed for using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT). The DUT includes a device memory having a number of input ports, and the FPGA is associated with a target memory having a second number of input ports, the second number being less than the first number. In one embodiment, a given set of inputs is applied to the device memory at a frequency Fd and in a defined cycle of time, and the given set of inputs is applied to the target memory at a frequency Ft. Ft is greater than Fd and cycle accuracy is maintained between the device memory and the target memory. In an embodiment, a cycle accurate model of the DUT memory is created by separating the DUT memory interface protocol from the target memory storage array."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator","description":"A method, system and computer program product are disclosed for using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT). The DUT includes a device memory havin","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10488460","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10488460","citation_suggestion":"Patentable. \"Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator\" (US-10488460). https://patentable.app/patents/US-10488460","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10488460","json":"https://patentable.app/api/llm-context/US-10488460","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T02:40:15.296Z"}