{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10489534","patent":{"patent_number":"US-10489534","title":"Support for multiple user defined assertion checkers in a multi-FPGA prototyping system","assignee":null,"inventors":[],"filing_date":"2019-03-20T00:00:00.000Z","publication_date":"2019-11-26T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F"],"num_claims":10,"abstract":"A method is provided that includes selecting an assertion checker for a design under test. The design under test includes hardware and firmware for a system on a chip, the method including instantiating the assertion checker in a compilation file, annotating the compilation file to define an assertion control signal for the assertion checker, and selecting one of a DISABLE or an ENABLE definition for the assertion control signal. The method also includes configuring a clock in a prototyping platform to stop when the assertion control signal is enabled in the assertion checker and a logic condition for the assertion control signal is satisfied in the prototyping platform. A system and a computer readable medium including instructions to perform the above method are also provided."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Support for multiple user defined assertion checkers in a multi-FPGA prototyping system","description":"A method is provided that includes selecting an assertion checker for a design under test. The design under test includes hardware and firmware for a system on a chip, the method including instantiati","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10489534","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10489534","citation_suggestion":"Patentable. \"Support for multiple user defined assertion checkers in a multi-FPGA prototyping system\" (US-10489534). https://patentable.app/patents/US-10489534","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10489534","json":"https://patentable.app/api/llm-context/US-10489534","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T15:58:06.932Z"}