{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10490242","patent":{"patent_number":"US-10490242","title":"Apparatus and method of clock shaping for memory","assignee":null,"inventors":[],"filing_date":"2018-11-30T00:00:00.000Z","publication_date":"2019-11-26T00:00:00.000Z","cpc_codes":["G11C"],"num_claims":9,"abstract":"A memory circuit according to some examples may include a clock delay circuit that use a polarity of a write enable signal to determine an operation (i.e. write or read) on the memory that provides the desired clock latency to the memory. The clock delay circuit may have a low skew portion and a high skew portion. The selection of the high skew portion or low skew portion may depend on the status of the write enable line, such as a polarity or logical value."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Apparatus and method of clock shaping for memory","description":"A memory circuit according to some examples may include a clock delay circuit that use a polarity of a write enable signal to determine an operation (i.e. write or read) on the memory that provides th","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10490242","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10490242","citation_suggestion":"Patentable. \"Apparatus and method of clock shaping for memory\" (US-10490242). https://patentable.app/patents/US-10490242","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10490242","json":"https://patentable.app/api/llm-context/US-10490242","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T07:41:30.150Z"}