{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10490273","patent":{"patent_number":"US-10490273","title":"Linearly weight updatable CMOS synaptic array without cell location dependence","assignee":null,"inventors":[],"filing_date":"2018-10-26T00:00:00.000Z","publication_date":"2019-11-26T00:00:00.000Z","cpc_codes":["G06N","G11C","G06N","G11C","G11C","G11C","G11C","G11C"],"num_claims":20,"abstract":"A neuromorphic circuit, chip, and method are provided. The neuromorphic circuit includes a crossbar synaptic array cell. The crossbar synaptic array cell includes a Complimentary Metal-Oxide-Semiconductor (CMOS) transistor having an on-resistance controlled by a gate voltage of the CMOS transistor to update a weight of the crossbar synaptic array cell. The neuromorphic circuit further includes a set of row-lines respectively connecting the synaptic array cell in series to a plurality of pre-synaptic neurons at first ends thereof. The neuromorphic circuit also includes a set of column-lines respectively connecting the synaptic array cell in series to a plurality of post-synaptic neurons at second ends thereof. The gate voltage of the CMOS transistor is controlled by performing a charge sharing technique that updates the weight of the crossbar synaptic array cell using non-overlapping pulses on control lines that are aligned with the set of row lines and the set of column lines."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Linearly weight updatable CMOS synaptic array without cell location dependence","description":"A neuromorphic circuit, chip, and method are provided. The neuromorphic circuit includes a crossbar synaptic array cell. The crossbar synaptic array cell includes a Complimentary Metal-Oxide-Semicondu","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10490273","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10490273","citation_suggestion":"Patentable. \"Linearly weight updatable CMOS synaptic array without cell location dependence\" (US-10490273). https://patentable.app/patents/US-10490273","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10490273","json":"https://patentable.app/api/llm-context/US-10490273","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T22:21:50.925Z"}