{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10490288","patent":{"patent_number":"US-10490288","title":"Page-level reference voltage parameterization for solid statesolid state storage devices","assignee":null,"inventors":[],"filing_date":"2018-09-27T00:00:00.000Z","publication_date":"2019-11-26T00:00:00.000Z","cpc_codes":["G11C","G06F","G06F","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":20,"abstract":"Page-level reference voltage parameterization techniques are provided for solid state memory devices. A method comprises obtaining a bit error count for a plurality of page numbers across a plurality of blocks of a solid state memory device; determining a substantially optimal reference voltage for each page number that substantially minimizes a corresponding bit error count; collecting, for each reference voltage, page numbers and corresponding substantially optimal reference voltages; and determining, for each reference voltage, a non-linear function that substantially fits a distribution of the collected page numbers and corresponding substantially optimal reference voltages, wherein a given page having a given page number is read using a plurality of parameters of the non-linear function to generate the substantially optimal reference voltage for the given page number. At least one additional page is optionally read using a mean value for the substantially optimal reference voltage for the page number of the additional page."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Page-level reference voltage parameterization for solid statesolid state storage devices","description":"Page-level reference voltage parameterization techniques are provided for solid state memory devices. A method comprises obtaining a bit error count for a plurality of page numbers across a plurality ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10490288","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10490288","citation_suggestion":"Patentable. \"Page-level reference voltage parameterization for solid statesolid state storage devices\" (US-10490288). https://patentable.app/patents/US-10490288","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10490288","json":"https://patentable.app/api/llm-context/US-10490288","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T23:03:27.613Z"}