{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10490471","patent":{"patent_number":"US-10490471","title":"Wafer-level packaging for enhanced performance","assignee":null,"inventors":[],"filing_date":"2018-05-30T00:00:00.000Z","publication_date":"2019-11-26T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":22,"abstract":"The present disclosure relates to a wafer-level packaging process. According to an exemplary process, a precursor wafer that includes a device layer with a number of input/output (I/O) contacts, a number of bump structures over the device layer, the stop layer underneath the device layer, and a silicon handle layer underneath the stop layer is provided. Herein, each bump structure is electronically coupled to a corresponding I/O contact. A first mold compound is then applied over the device layer to encapsulate each bump structure. Next, the silicon handle layer is removed substantially. A second mold compound is applied to an exposed surface from which the silicon handle layer was removed. Finally, the first mold compound is thinned down to expose a portion of each bump structure."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Wafer-level packaging for enhanced performance","description":"The present disclosure relates to a wafer-level packaging process. According to an exemplary process, a precursor wafer that includes a device layer with a number of input/output (I/O) contacts, a num","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10490471","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10490471","citation_suggestion":"Patentable. \"Wafer-level packaging for enhanced performance\" (US-10490471). https://patentable.app/patents/US-10490471","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10490471","json":"https://patentable.app/api/llm-context/US-10490471","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T04:20:36.930Z"}