{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10490530","patent":{"patent_number":"US-10490530","title":"Stacked semiconductor chips having transistor in a boundary region","assignee":null,"inventors":[],"filing_date":"2017-10-31T00:00:00.000Z","publication_date":"2019-11-26T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":20,"abstract":"A semiconductor package and a method for fabricating the same are provided. The semiconductor package includes a first semiconductor chip which includes a first region, a second region, and a boundary region between the first region and the second region; and a second semiconductor chip disposed on the first semiconductor chip, wherein the second semiconductor chip is overlapping the first region and a part of the boundary region, and not overlapping the second region, wherein a first circuit element is disposed in the first region and a second circuit element is disposed in the boundary region, and wherein second circuit element stress tolerance is greater than first circuit element stress tolerance."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Stacked semiconductor chips having transistor in a boundary region","description":"A semiconductor package and a method for fabricating the same are provided. The semiconductor package includes a first semiconductor chip which includes a first region, a second region, and a boundary","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10490530","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10490530","citation_suggestion":"Patentable. \"Stacked semiconductor chips having transistor in a boundary region\" (US-10490530). https://patentable.app/patents/US-10490530","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10490530","json":"https://patentable.app/api/llm-context/US-10490530","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T22:16:51.199Z"}