{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10490544","patent":{"patent_number":"US-10490544","title":"Memory circuit layout","assignee":null,"inventors":[],"filing_date":"2018-01-05T00:00:00.000Z","publication_date":"2019-11-26T00:00:00.000Z","cpc_codes":["G06F","H01L","H01L"],"num_claims":20,"abstract":"A memory circuit layout design includes first, second, third, and fourth memory cell regions abutting one another and corresponding to respective first, second, third, and fourth memory cells of the memory circuit. A first oxide diffusion (OD) layout pattern corresponds to a first active structure for forming the first and second memory cells, extends along a first direction, and has a shared source portion overlapping the first and second memory cell regions. A second OD layout pattern corresponds to a second active structure for forming the third and fourth memory cells, extends along the first direction, and has a shared source portion overlapping the third and fourth memory cell regions. A first conductive layout pattern corresponds to a first conductive structure under a lowest via plug layer of the memory circuit, extends along a second direction, and overlaps the shared source portions of the first and second OD layout patterns."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory circuit layout","description":"A memory circuit layout design includes first, second, third, and fourth memory cell regions abutting one another and corresponding to respective first, second, third, and fourth memory cells of the m","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10490544","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10490544","citation_suggestion":"Patentable. \"Memory circuit layout\" (US-10490544). https://patentable.app/patents/US-10490544","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10490544","json":"https://patentable.app/api/llm-context/US-10490544","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T09:24:38.748Z"}