{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10496422","patent":{"patent_number":"US-10496422","title":"Serial device emulator using two memory levels with dynamic and configurable response","assignee":null,"inventors":[],"filing_date":"2016-11-11T00:00:00.000Z","publication_date":"2019-12-03T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G11C","G11C","G11C","G06F","G06F"],"num_claims":20,"abstract":"A digital logic device is disclosed that includes registers, SRAM, DRAM, and a processor configured to store in the registers an initial portion of a first response data to a command, and store in the SRAM the first response data. The processor is further configured to store in a lookup table the memory location and size of the first response data in the SRAM, store in the DRAM additional response data, and store in the lookup table the memory location and size of the additional response data in the DRAM. The processor is configured to receive the command from a host device, retrieve the first response data from the registers or the SRAM, and send the first response data to the host. If the command includes additional response data, the processor is configured to concurrently retrieve the additional response data from DRAM and send the additional response data to the host."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Serial device emulator using two memory levels with dynamic and configurable response","description":"A digital logic device is disclosed that includes registers, SRAM, DRAM, and a processor configured to store in the registers an initial portion of a first response data to a command, and store in the","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10496422","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10496422","citation_suggestion":"Patentable. \"Serial device emulator using two memory levels with dynamic and configurable response\" (US-10496422). https://patentable.app/patents/US-10496422","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10496422","json":"https://patentable.app/api/llm-context/US-10496422","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T20:34:00.997Z"}