{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10496561","patent":{"patent_number":"US-10496561","title":"Resilient vertical stacked chip network for routing memory requests to a plurality of memory dies","assignee":null,"inventors":[],"filing_date":"2017-04-18T00:00:00.000Z","publication_date":"2019-12-03T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":20,"abstract":"Systems, apparatuses, and methods for routing traffic through vertically stacked memory are disclosed. A computing system includes a host processor die and multiple vertically stacked memory dies. The host processor die generates memory access requests for the data stored in the multiple memory array banks in the memory dies. At least one memory die uses an on-die network switch with a programmable routing table for routing packets corresponding to the generated memory requests. Routes use both vertical hops and horizontal hops to reach the target memory array bank and to avoid any congested or failed resources along the route. The vertically stacked memory dies use through silicon via interconnects and at least one via does not traverse through all of the memory dies. Accordingly, the host processor die does not have a direct connection to one or more of the multiple memory dies."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Resilient vertical stacked chip network for routing memory requests to a plurality of memory dies","description":"Systems, apparatuses, and methods for routing traffic through vertically stacked memory are disclosed. A computing system includes a host processor die and multiple vertically stacked memory dies. The","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10496561","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10496561","citation_suggestion":"Patentable. \"Resilient vertical stacked chip network for routing memory requests to a plurality of memory dies\" (US-10496561). https://patentable.app/patents/US-10496561","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10496561","json":"https://patentable.app/api/llm-context/US-10496561","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T14:11:59.397Z"}