{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10496565","patent":{"patent_number":"US-10496565","title":"Micro-architectural techniques to minimize companion die firmware loading times in a server platform","assignee":null,"inventors":[],"filing_date":"2018-07-30T00:00:00.000Z","publication_date":"2019-12-03T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F"],"num_claims":18,"abstract":"Examples include an apparatus having a communications link bridge coupled to a plurality of processors to control connections between each of the plurality of processors and the apparatus; and a controller coupled to a memory over a memory interface to control access to the memory, the controller configured to, during system initialization, selectively bypass a token requirement for access to the memory for read requests by processors and allow multiple processors to read the memory concurrently."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Micro-architectural techniques to minimize companion die firmware loading times in a server platform","description":"Examples include an apparatus having a communications link bridge coupled to a plurality of processors to control connections between each of the plurality of processors and the apparatus; and a contr","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10496565","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10496565","citation_suggestion":"Patentable. \"Micro-architectural techniques to minimize companion die firmware loading times in a server platform\" (US-10496565). https://patentable.app/patents/US-10496565","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10496565","json":"https://patentable.app/api/llm-context/US-10496565","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T10:32:54.955Z"}