{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10497408","patent":{"patent_number":"US-10497408","title":"Memory circuit including overlay memory cells and method of operating thereof","assignee":null,"inventors":[],"filing_date":"2017-12-05T00:00:00.000Z","publication_date":"2019-12-03T00:00:00.000Z","cpc_codes":["G11C","G06F","G06F","G06F","G11C","G11C","G11C","G11C","G11C"],"num_claims":12,"abstract":"A memory circuit may include a plurality of electrically programmable memory cells arranged in an electrically programmable non-volatile memory cell array along a plurality of rows and a plurality of columns, a plurality of word lines, each word line coupled with a plurality of word portions of the plurality of memory cells, each word portion configured to store a data word, and at least one overlay word line coupled with a plurality of overlay portions, each overlay portion including overlay memory cells, each of the plurality of overlay portions including an overlay word. The memory circuit is configured to read, for each of the plurality of word lines, from each of the word portions simultaneously with an overlay portion of the plurality of overlay portions, with an output of the read operation being a result of a logic operation performed on the data word and the overlay word."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory circuit including overlay memory cells and method of operating thereof","description":"A memory circuit may include a plurality of electrically programmable memory cells arranged in an electrically programmable non-volatile memory cell array along a plurality of rows and a plurality of ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10497408","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10497408","citation_suggestion":"Patentable. \"Memory circuit including overlay memory cells and method of operating thereof\" (US-10497408). https://patentable.app/patents/US-10497408","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10497408","json":"https://patentable.app/api/llm-context/US-10497408","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T15:37:50.171Z"}