{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10497420","patent":{"patent_number":"US-10497420","title":"Memory with internal refresh rate control","assignee":null,"inventors":[],"filing_date":"2018-05-08T00:00:00.000Z","publication_date":"2019-12-03T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":22,"abstract":"Memory devices, systems including memory devices, and methods of operating memory devices in which redundancy match is disabled to permit activating more word lines in parallel during refresh operations to increase a refresh rate of memory cells in a memory array. In one embodiment, a memory device is provided, comprising a memory array including a plurality of word lines arranged in a plurality of memory banks. The memory device further comprises circuitry configured to (i) store a value indicating one or more addresses corresponding to word lines in the plurality of word lines, (ii) disable redundancy match, (iii) activate one or more first word lines in the memory array corresponding to the one or more addresses indicated by the value to refresh first data stored in the memory array, and (iv) update the value based at least in part on activating the one or more first word lines."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory with internal refresh rate control","description":"Memory devices, systems including memory devices, and methods of operating memory devices in which redundancy match is disabled to permit activating more word lines in parallel during refresh operatio","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10497420","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10497420","citation_suggestion":"Patentable. \"Memory with internal refresh rate control\" (US-10497420). https://patentable.app/patents/US-10497420","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10497420","json":"https://patentable.app/api/llm-context/US-10497420","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T00:37:46.334Z"}