{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10497627","patent":{"patent_number":"US-10497627","title":"Method of manufacturing a dopant transistor located vertically on the gate","assignee":null,"inventors":[],"filing_date":"2017-02-01T00:00:00.000Z","publication_date":"2019-12-03T00:00:00.000Z","cpc_codes":["H01L","H01L"],"num_claims":17,"abstract":"A method is provided for forming a transistor from a stack including the following successive layers: an electrically insulating layer, an active zone including at least one semiconductor layer, and a gate, sides of which are configured to be covered by at least one spacer, the method including: a phase of forming lateral cavities; and forming a raised drain and a raised source that fill the lateral cavities by growing the semiconductor layer via epitaxy, the forming of the lateral cavities includes, after a step of partially removing the semiconductor layer: forming a sacrificial layer, partially removing the sacrificial layer; forming spacers against the sides of the gate resting on a residual sacrificial layer; and totally removing the residual sacrificial layer in order to form the lateral cavities."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method of manufacturing a dopant transistor located vertically on the gate","description":"A method is provided for forming a transistor from a stack including the following successive layers: an electrically insulating layer, an active zone including at least one semiconductor layer, and a","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10497627","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10497627","citation_suggestion":"Patentable. \"Method of manufacturing a dopant transistor located vertically on the gate\" (US-10497627). https://patentable.app/patents/US-10497627","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10497627","json":"https://patentable.app/api/llm-context/US-10497627","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T10:08:40.918Z"}