{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10497812","patent":{"patent_number":"US-10497812","title":"Transistor array panel","assignee":null,"inventors":[],"filing_date":"2017-02-17T00:00:00.000Z","publication_date":"2019-12-03T00:00:00.000Z","cpc_codes":["G02F","G02F","G02F","G02F","G02F"],"num_claims":27,"abstract":"A transistor is positioned on a substrate. The transistor includes a semiconductor layer. A buffer layer is positioned between the substrate and the semiconductor layer of the transistor, including an insulating material. A bottom layer is positioned between the substrate and the buffer layer. The bottom layer and the semiconductor layer overlap each other. The bottom layer includes a first layer, a second layer, and a third layer that are stacked on each other in a direction away from the substrate."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Transistor array panel","description":"A transistor is positioned on a substrate. The transistor includes a semiconductor layer. A buffer layer is positioned between the substrate and the semiconductor layer of the transistor, including an","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10497812","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10497812","citation_suggestion":"Patentable. \"Transistor array panel\" (US-10497812). https://patentable.app/patents/US-10497812","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10497812","json":"https://patentable.app/api/llm-context/US-10497812","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T17:19:26.637Z"}