{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10503514","patent":{"patent_number":"US-10503514","title":"Method for implementing a reduced size register view data structure in a microprocessor","assignee":null,"inventors":[],"filing_date":"2017-11-07T00:00:00.000Z","publication_date":"2019-12-10T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F","G06F","G06F"],"num_claims":20,"abstract":"A method of managing a reduced size register view data structure in a processor, where the method includes receiving an incoming instruction sequence using a global front end, grouping instructions from the incoming instruction sequence to form instruction blocks, populating a register view data structure, wherein the register view data structure stores register information references by the instruction blocks as a set of register templates, generating a set of snapshots of the register templates to reduce a size of the register view data structure, and tracking a state of the processor to handle a branch miss-prediction using the register view data structure in accordance with execution of the instruction blocks."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method for implementing a reduced size register view data structure in a microprocessor","description":"A method of managing a reduced size register view data structure in a processor, where the method includes receiving an incoming instruction sequence using a global front end, grouping instructions fr","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10503514","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10503514","citation_suggestion":"Patentable. \"Method for implementing a reduced size register view data structure in a microprocessor\" (US-10503514). https://patentable.app/patents/US-10503514","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10503514","json":"https://patentable.app/api/llm-context/US-10503514","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T09:28:55.613Z"}