{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10503589","patent":{"patent_number":"US-10503589","title":"Semiconductor memory devices, memory systems and methods of operating semiconductor memory devices","assignee":null,"inventors":[],"filing_date":"2018-06-29T00:00:00.000Z","publication_date":"2019-12-10T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G11C","G11C"],"num_claims":20,"abstract":"Semiconductor memory device may include a memory cell array, an error correction circuit, an input/output (I/O) gating circuit and a control logic circuit. The control logic circuit may, in a first write operation mode, control the I/O gating circuit to select a sub-page, read a first unit of data including a first sub unit of data, a second sub unit of data and a first parity data from the sub-page, and provide the first unit of data to the error correction circuit. The control logic circuit may also control the error correction circuit to perform an error-correcting code decoding on the first unit of data to generate syndrome data, generate second parity data based on a portion of the first unit of data and generate third parity data based on a write parity data, the second parity data and the syndrome data."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Semiconductor memory devices, memory systems and methods of operating semiconductor memory devices","description":"Semiconductor memory device may include a memory cell array, an error correction circuit, an input/output (I/O) gating circuit and a control logic circuit. The control logic circuit may, in a first wr","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10503589","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10503589","citation_suggestion":"Patentable. \"Semiconductor memory devices, memory systems and methods of operating semiconductor memory devices\" (US-10503589). https://patentable.app/patents/US-10503589","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10503589","json":"https://patentable.app/api/llm-context/US-10503589","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T23:03:20.035Z"}