{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10504587","patent":{"patent_number":"US-10504587","title":"Method and system for compensating for floating gate-to-floating gate (fg-fg) interference in flash memory cell read operations","assignee":null,"inventors":[],"filing_date":"2017-12-20T00:00:00.000Z","publication_date":"2019-12-10T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":19,"abstract":"Embodiments of the present disclosure provide methods, devices, modules, and systems for compensating for floating gate to floating gate (fg-fg) interference in flash memory cell read operations. Compensating for fg-fg interference effects can reduce or prevent read errors. Embodiments of the present disclosure can compensate for fg-fg interference by determining the programmed state of aggressor (or influencing) memory cells that are programmed after a target memory cell. If the aggressor memory cell is in the erased state of Level 0 or is in a programmed state of Level 2-15, the target memory cell is identified as undisturbed. If the aggressor memory cell is programmed to a Level 1 (instead of Level 0 or Levels 2-15), the target memory cell is identified as disturbed. If the target memory cell is disturbed, sensing parameters may be adjusted to compensate for the disruption."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method and system for compensating for floating gate-to-floating gate (fg-fg) interference in flash memory cell read operations","description":"Embodiments of the present disclosure provide methods, devices, modules, and systems for compensating for floating gate to floating gate (fg-fg) interference in flash memory cell read operations. Comp","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10504587","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10504587","citation_suggestion":"Patentable. \"Method and system for compensating for floating gate-to-floating gate (fg-fg) interference in flash memory cell read operations\" (US-10504587). https://patentable.app/patents/US-10504587","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10504587","json":"https://patentable.app/api/llm-context/US-10504587","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T10:32:39.543Z"}