{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10504777","patent":{"patent_number":"US-10504777","title":"Method of manufacturing wafer level low melting temperature interconnections","assignee":null,"inventors":[],"filing_date":"2018-02-13T00:00:00.000Z","publication_date":"2019-12-10T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":17,"abstract":"A method of manufacturing an array of planar wafer level metal posts includes plating an array of posts within a photoresist (PR) pattern mold on a substrate of a first wafer. Stripping the PR pattern mold from the substrate and array of posts. Applying an oxide layer, at a temperature of below 150 degrees Celsius, over a surface of the first wafer. Applying chemical-mechanical polishing (CMP) to planarize the oxide layer and the array of posts."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Method of manufacturing wafer level low melting temperature interconnections","description":"A method of manufacturing an array of planar wafer level metal posts includes plating an array of posts within a photoresist (PR) pattern mold on a substrate of a first wafer. Stripping the PR pattern","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10504777","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10504777","citation_suggestion":"Patentable. \"Method of manufacturing wafer level low melting temperature interconnections\" (US-10504777). https://patentable.app/patents/US-10504777","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10504777","json":"https://patentable.app/api/llm-context/US-10504777","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T13:24:26.897Z"}