{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10504794","patent":{"patent_number":"US-10504794","title":"Self-aligned silicide/germanide formation to reduce external resistance in a vertical field-effect transistor","assignee":null,"inventors":[],"filing_date":"2018-06-25T00:00:00.000Z","publication_date":"2019-12-10T00:00:00.000Z","cpc_codes":["H01L","H01L"],"num_claims":15,"abstract":"A method for manufacturing a vertical transistor device includes respectively forming a first and second plurality of fins in first and second device regions on a substrate. A plurality of bottom source/drain regions are formed adjacent lower portions of each of the fins, and a sacrificial layer is formed in the first device region on a first bottom source/drain region of the plurality of bottom source/drain regions. In the method, gate structures are formed on the bottom source/drain regions and sacrificial layer, and portions of the gate structures are removed to expose the sacrificial layer in the first device region and a second bottom source/drain region of the plurality of bottom source/drain regions in the second device region. The method further includes depositing a germanium oxide layer on the exposed sacrificial layer and second bottom source/drain region, and converting the germanium oxide layer to a plurality of silicide/germanide layers."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Self-aligned silicide/germanide formation to reduce external resistance in a vertical field-effect transistor","description":"A method for manufacturing a vertical transistor device includes respectively forming a first and second plurality of fins in first and second device regions on a substrate. A plurality of bottom sour","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10504794","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10504794","citation_suggestion":"Patentable. \"Self-aligned silicide/germanide formation to reduce external resistance in a vertical field-effect transistor\" (US-10504794). https://patentable.app/patents/US-10504794","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10504794","json":"https://patentable.app/api/llm-context/US-10504794","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T14:10:47.283Z"}