{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10504909","patent":{"patent_number":"US-10504909","title":"Plate node configurations and operations for a memory array","assignee":null,"inventors":[],"filing_date":"2018-05-02T00:00:00.000Z","publication_date":"2019-12-10T00:00:00.000Z","cpc_codes":["G11C","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":23,"abstract":"Methods, systems, and devices for plate node configurations and operations for a memory array are described. A single plate node of a memory array may be coupled to multiple rows or columns of memory cells (e.g., ferroelectric memory cells) in a deck of memory cells. The single plate node may perform the functions of multiple plate nodes. The number of contacts to couple the single plate node to the substrate may be less than the number of contacts to couple multiple plate nodes to the substrate. Connectors or sockets in a memory array with a single plate node may define a size that is less than a size of the connectors or sockets with multiple plate nodes. In some examples, a single plate node of the memory array may be coupled to multiple lines of a memory cells in multiple decks of memory cells."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Plate node configurations and operations for a memory array","description":"Methods, systems, and devices for plate node configurations and operations for a memory array are described. A single plate node of a memory array may be coupled to multiple rows or columns of memory ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10504909","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10504909","citation_suggestion":"Patentable. \"Plate node configurations and operations for a memory array\" (US-10504909). https://patentable.app/patents/US-10504909","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10504909","json":"https://patentable.app/api/llm-context/US-10504909","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T10:32:13.997Z"}