{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10509655","patent":{"patent_number":"US-10509655","title":"Processor circuit and operation method thereof","assignee":null,"inventors":[],"filing_date":"2018-08-22T00:00:00.000Z","publication_date":"2019-12-17T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F"],"num_claims":20,"abstract":"A processor circuit and an operation method thereof are provided. The processor circuit includes a re-order buffer (ROB) and an alias queue (AQ) module. The ROB records next sequential instruction pointer (Nsip) values of a plurality of load instructions and a plurality of store instructions. Each of a plurality of entries of the AQ module includes a first field and a plurality of second fields. When a first load instruction and a first store instruction cause a first memory violation and the ROB retires the first load instruction, the AQ module stores the Nsip value of the first load instruction into the first field of one of the entries and stores the Nsip value of the first store instruction into one of the second fields of one of the entries."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Processor circuit and operation method thereof","description":"A processor circuit and an operation method thereof are provided. The processor circuit includes a re-order buffer (ROB) and an alias queue (AQ) module. The ROB records next sequential instruction poi","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10509655","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10509655","citation_suggestion":"Patentable. \"Processor circuit and operation method thereof\" (US-10509655). https://patentable.app/patents/US-10509655","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10509655","json":"https://patentable.app/api/llm-context/US-10509655","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T17:18:54.185Z"}