{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10509713","patent":{"patent_number":"US-10509713","title":"Observation by a debug host with memory model and timing offset calculation between instruction and data traces of software execution carried on in a debug target having a main memory and a cache arrangement","assignee":null,"inventors":[],"filing_date":"2015-08-18T00:00:00.000Z","publication_date":"2019-12-17T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F"],"num_claims":18,"abstract":"A method, performed in a debug host, for observing software execution on a computer having one or more processor cores, a cache attached to the one or more processor cores via respective execution pipelines forming a cache arrangement, and a memory, comprises obtaining an instruction trace of the cache arrangement and a data trace for data being loaded from the memory into the cache. The instruction trace is synchronized with the data trace to generate a synchronized data trace and/or a synchronized instruction trace. A state of a memory model, representing a memory readable by the one or more processor cores via a respective instruction is updated using the synchronized data trace and the synchronized instruction trace."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Observation by a debug host with memory model and timing offset calculation between instruction and data traces of software execution carried on in a debug target having a main memory and a cache arrangement","description":"A method, performed in a debug host, for observing software execution on a computer having one or more processor cores, a cache attached to the one or more processor cores via respective execution pip","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10509713","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10509713","citation_suggestion":"Patentable. \"Observation by a debug host with memory model and timing offset calculation between instruction and data traces of software execution carried on in a debug target having a main memory and a cache arrangement\" (US-10509713). https://patentable.app/patents/US-10509713","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10509713","json":"https://patentable.app/api/llm-context/US-10509713","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T10:34:28.994Z"}