{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10509876","patent":{"patent_number":"US-10509876","title":"Simulation using parallel processors","assignee":null,"inventors":[],"filing_date":"2015-06-03T00:00:00.000Z","publication_date":"2019-12-17T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F"],"num_claims":18,"abstract":"A method for design simulation includes partitioning a verification task of a design (100) into a first plurality of atomic Processing Elements (PEs—108) having execution dependencies (112), each execution dependency specifying that a respective first PE is to be executed before a respective second PE. The method further includes computing an order for executing the PEs on a multiprocessor device (32), which includes a second plurality of processors (44) operating in parallel and schedules the PEs for execution by the processors according to a built-in scheduling policy. The order induces concurrent execution of the PEs by different ones of the processors without violating the execution dependencies, irrespective of the scheduling policy. The PEs are executed on the processors in accordance with the computed order and the scheduling policy, to produce a simulation result. A performance of the design is verified responsively to the simulation result."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Simulation using parallel processors","description":"A method for design simulation includes partitioning a verification task of a design (100) into a first plurality of atomic Processing Elements (PEs—108) having execution dependencies (112), each exec","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10509876","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10509876","citation_suggestion":"Patentable. \"Simulation using parallel processors\" (US-10509876). https://patentable.app/patents/US-10509876","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10509876","json":"https://patentable.app/api/llm-context/US-10509876","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T21:47:23.551Z"}