{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10510597","patent":{"patent_number":"US-10510597","title":"Methods for hybrid wafer bonding integrated with CMOS processing","assignee":null,"inventors":[],"filing_date":"2017-08-07T00:00:00.000Z","publication_date":"2019-12-17T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":20,"abstract":"Methods for forming an integrated device using CMOS processing with wafer bonding. In an embodiment, a method is disclosed that includes defining an integrated circuit function using a front-end substrate having one or more active devices and a back-end substrate having connections formed in metal layers in dielectric material, wherein the back-end substrate is free from active devices; manufacturing the front-end substrate in a first semiconductor process; more or less simultaneously, manufacturing the back-end substrate in a second semiconductor process; physically contacting bonding surfaces of the front-end substrate and the back-end substrate; and performing wafer bonding to form bonds between the front-end and back-end substrates to form an integrated circuit. Additional methods are disclosed."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Methods for hybrid wafer bonding integrated with CMOS processing","description":"Methods for forming an integrated device using CMOS processing with wafer bonding. In an embodiment, a method is disclosed that includes defining an integrated circuit function using a front-end subst","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10510597","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10510597","citation_suggestion":"Patentable. \"Methods for hybrid wafer bonding integrated with CMOS processing\" (US-10510597). https://patentable.app/patents/US-10510597","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10510597","json":"https://patentable.app/api/llm-context/US-10510597","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T20:36:32.572Z"}