{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10510651","patent":{"patent_number":"US-10510651","title":"Hard macro having blockage sites, integrated circuit including same and method of routing through a hard macro","assignee":null,"inventors":[],"filing_date":"2018-12-14T00:00:00.000Z","publication_date":"2019-12-17T00:00:00.000Z","cpc_codes":["H01L","G06F","H01L","H01L"],"num_claims":6,"abstract":"A hard macro includes a periphery defining a hard macro area and having a top and a bottom and a hard macro thickness from the top to the bottom, the hard macro including a plurality of vias extending through the hard macro thickness from the top to the bottom. Also an integrated circuit having a top layer, a bottom layer and at least one middle layer, the top layer including a top layer conductive trace, the middle layer including a hard macro and the bottom layer including a bottom layer conductive trace, wherein the top layer conductive trace is connected to the bottom layer conductive trace by a via extending through the hard macro."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Hard macro having blockage sites, integrated circuit including same and method of routing through a hard macro","description":"A hard macro includes a periphery defining a hard macro area and having a top and a bottom and a hard macro thickness from the top to the bottom, the hard macro including a plurality of vias extending","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10510651","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10510651","citation_suggestion":"Patentable. \"Hard macro having blockage sites, integrated circuit including same and method of routing through a hard macro\" (US-10510651). https://patentable.app/patents/US-10510651","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10510651","json":"https://patentable.app/api/llm-context/US-10510651","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T11:17:20.992Z"}