{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10510744","patent":{"patent_number":"US-10510744","title":"Vertical nanowire transistor for input/output structure","assignee":null,"inventors":[],"filing_date":"2017-08-14T00:00:00.000Z","publication_date":"2019-12-17T00:00:00.000Z","cpc_codes":["H01L","H01L"],"num_claims":20,"abstract":"An electrostatic discharge (ESD) protection circuit includes an input terminal, a transistor, and an output terminal. The input terminal is configured to receive an input signal. The transistor includes a first source/drain region, a second source/drain region, and a drift region that has a resistance in series between the first and second source/drain regions and that is configured to attenuate an ESD voltage in the input signal. The output terminal is connected to the second source/drain region."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Vertical nanowire transistor for input/output structure","description":"An electrostatic discharge (ESD) protection circuit includes an input terminal, a transistor, and an output terminal. The input terminal is configured to receive an input signal. The transistor includ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10510744","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10510744","citation_suggestion":"Patentable. \"Vertical nanowire transistor for input/output structure\" (US-10510744). https://patentable.app/patents/US-10510744","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10510744","json":"https://patentable.app/api/llm-context/US-10510744","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T00:17:17.889Z"}