{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10510766","patent":{"patent_number":"US-10510766","title":"Flash memory structure with reduced dimension of gate structure and methods of forming thereof","assignee":null,"inventors":[],"filing_date":"2019-05-24T00:00:00.000Z","publication_date":"2019-12-17T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":20,"abstract":"A method for forming a semiconductor memory device structure includes forming a select gate structure and a dielectric layer, forming a charge trapping layer along a sidewall of a lower portion of the select gate structure and a sidewall of the dielectric layer, and forming a memory gate structure over the charge trapping layer. The select gate structure and the memory gate structure contact opposing sidewalls of the charge trapping layer. The dielectric layer is interposed between the charge trapping layer and the select gate structure."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Flash memory structure with reduced dimension of gate structure and methods of forming thereof","description":"A method for forming a semiconductor memory device structure includes forming a select gate structure and a dielectric layer, forming a charge trapping layer along a sidewall of a lower portion of the","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10510766","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10510766","citation_suggestion":"Patentable. \"Flash memory structure with reduced dimension of gate structure and methods of forming thereof\" (US-10510766). https://patentable.app/patents/US-10510766","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10510766","json":"https://patentable.app/api/llm-context/US-10510766","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T09:35:30.872Z"}