{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10514983","patent":{"patent_number":"US-10514983","title":"Memory apparatus with redundancy array","assignee":null,"inventors":[],"filing_date":"2017-04-26T00:00:00.000Z","publication_date":"2019-12-24T00:00:00.000Z","cpc_codes":["G06F","G06F","G11C","G11C","G11C","G11C","G11C","G11C"],"num_claims":16,"abstract":"Apparatuses and methods for memory repair for a memory device are described. An example apparatus includes: a data input/output circuit that provides data via a plurality of data signal lines; memory cell arrays; an ECC/Parity redundancy array; and a redundancy circuit coupled to the plurality of data signal lines. The redundancy circuit includes an error correction block that generates error correction information based on the data and provides the error correction information to the ECC/Parity redundancy array. If during test it is determined that a failure is not repairable by standard redundancy including error correction code, the error correction parity array is not needed and can be redirected by a block repair circuit. The error correction circuit can now have its functionality changed to allow the error correction array to become a block repair."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Memory apparatus with redundancy array","description":"Apparatuses and methods for memory repair for a memory device are described. An example apparatus includes: a data input/output circuit that provides data via a plurality of data signal lines; memory ","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10514983","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10514983","citation_suggestion":"Patentable. \"Memory apparatus with redundancy array\" (US-10514983). https://patentable.app/patents/US-10514983","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10514983","json":"https://patentable.app/api/llm-context/US-10514983","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T21:10:20.377Z"}