{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10515008","patent":{"patent_number":"US-10515008","title":"Performance based memory block usage","assignee":null,"inventors":[],"filing_date":"2017-10-25T00:00:00.000Z","publication_date":"2019-12-24T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F","G06F","G11C","G11C","G11C","G06F","G06F","G06F"],"num_claims":18,"abstract":"Blocks of memory cells may be selected for use based on one or more measured performance characteristics that may include, but are not limited to, programming time or fail bit count. Blocks may be placed into a single level cell (SLC) block pool and one or more multi-level cell (MLC) block pools based on measured performance characteristic(s). For example, blocks that have a better SLC performance may be placed into the SLC block pool. Blocks may be targeted for garbage collection based on one or more measured performance characteristics. For example, blocks within an SLC block pool may be targeted for garbage collection based on a performance ranking of the SLC blocks, blocks within an MLC block pool may be targeted for garbage collection based on a performance ranking of the MLC blocks. Thus, the better performing blocks may be used more frequently, thereby improving performance."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Performance based memory block usage","description":"Blocks of memory cells may be selected for use based on one or more measured performance characteristics that may include, but are not limited to, programming time or fail bit count. Blocks may be pla","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10515008","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10515008","citation_suggestion":"Patentable. \"Performance based memory block usage\" (US-10515008). https://patentable.app/patents/US-10515008","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10515008","json":"https://patentable.app/api/llm-context/US-10515008","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T04:20:29.679Z"}