{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10515170","patent":{"patent_number":"US-10515170","title":"Deep insight for debug using internal equivalence visualization and counter-example for sequential equivalence checking","assignee":null,"inventors":[],"filing_date":"2018-07-12T00:00:00.000Z","publication_date":"2019-12-24T00:00:00.000Z","cpc_codes":["G06F","G06F","G06F","G06F","G06F"],"num_claims":20,"abstract":"Disclosed is a technology for parallelized design verification of two circuit designs at a register transfer level. A plurality of potential equivalent sub-circuit pairs is identified from the circuit designs to create a proof-tree structure. The proof-tree structure includes a root-proof, a plurality of parent-proofs downchain of said root-proof and a plurality of child-proofs downchain of at least one of the parent-proofs. Each one of the child-proofs is associated with a first equivalency status of one of the potential equivalent sub-circuit pairs. The parent-proofs are associated with second equivalency statuses dependent upon the first equivalency statuses of downchain child-proofs. The root-proof is associated with a third functional equivalency status of the two circuit designs dependent upon the second equivalency statuses of downchain parent-proofs. This Abstract is not intended to limit the scope of the claims."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Deep insight for debug using internal equivalence visualization and counter-example for sequential equivalence checking","description":"Disclosed is a technology for parallelized design verification of two circuit designs at a register transfer level. A plurality of potential equivalent sub-circuit pairs is identified from the circuit","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10515170","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10515170","citation_suggestion":"Patentable. \"Deep insight for debug using internal equivalence visualization and counter-example for sequential equivalence checking\" (US-10515170). https://patentable.app/patents/US-10515170","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10515170","json":"https://patentable.app/api/llm-context/US-10515170","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-31T00:18:49.855Z"}