{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10515810","patent":{"patent_number":"US-10515810","title":"Self-aligned di-silicon silicide bit line and source line landing pads in 3D vertical channel memory","assignee":null,"inventors":[],"filing_date":"2018-04-10T00:00:00.000Z","publication_date":"2019-12-24T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L"],"num_claims":17,"abstract":"A method for manufacturing a memory device comprises forming an initial silicide layer, including depositing and annealing a precursor metal over a layer of silicon material on a top surface of a stack of conductive strips in amounts effective to result in a majority of the initial silicide layer being a mono-silicon silicide of the precursor metal. The method comprises depositing and annealing additional silicon material over the initial silicide layer in amounts effective to result in formation of di-silicon silicide of the precursor metal to form a landing pad on the top surface of the stack of conductive strips, the formation of the di-silicon silicide of the precursor metal consuming mono-silicon silicide of the initial silicide layer so a majority of a silicide of the landing pad is di-silicon silicide."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Self-aligned di-silicon silicide bit line and source line landing pads in 3D vertical channel memory","description":"A method for manufacturing a memory device comprises forming an initial silicide layer, including depositing and annealing a precursor metal over a layer of silicon material on a top surface of a stac","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10515810","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10515810","citation_suggestion":"Patentable. \"Self-aligned di-silicon silicide bit line and source line landing pads in 3D vertical channel memory\" (US-10515810). https://patentable.app/patents/US-10515810","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10515810","json":"https://patentable.app/api/llm-context/US-10515810","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T12:44:18.027Z"}