{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10515914","patent":{"patent_number":"US-10515914","title":"Sintered solder for fine pitch first-level interconnect (FLI) applications","assignee":null,"inventors":[],"filing_date":"2019-01-29T00:00:00.000Z","publication_date":"2019-12-24T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":19,"abstract":"Foundation layers and methods of forming a foundation layer are described. Die pads are formed over a die. A dielectric layer is formed over die pads and the die. The dielectric layer is then recessed to expose top portions of the die pads. A first plurality of sintered conductive vias are formed over the die pads. The first sintered conductive vias are coupled to at least one of the die pads. In addition, a photoresist layer may be formed over the dielectric layer and the top portions of the die pads. Via openings are formed in the photoresist layer. A second plurality of sintered conductive vias may then be formed over the first sintered conductive vias to form a plurality of sintered conductive lines. Each of the first and second sintered conductive vias are formed with a liquid phase sintering (LPS) solder paste."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"Sintered solder for fine pitch first-level interconnect (FLI) applications","description":"Foundation layers and methods of forming a foundation layer are described. Die pads are formed over a die. A dielectric layer is formed over die pads and the die. The dielectric layer is then recessed","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10515914","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10515914","citation_suggestion":"Patentable. \"Sintered solder for fine pitch first-level interconnect (FLI) applications\" (US-10515914). https://patentable.app/patents/US-10515914","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10515914","json":"https://patentable.app/api/llm-context/US-10515914","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T12:44:28.298Z"}