{"schema_version":"1.0","canonical_url":"https://patentable.app/patents/US-10515920","patent":{"patent_number":"US-10515920","title":"High bandwidth memory package for high performance processors","assignee":null,"inventors":[],"filing_date":"2018-04-09T00:00:00.000Z","publication_date":"2019-12-24T00:00:00.000Z","cpc_codes":["H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","G11C","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L","H01L"],"num_claims":10,"abstract":"Integrated component packages and methods of assembling integrated component packages are provided. The integrated component package can comprise a bump pitch relaxing layer. A high-bandwidth memory component directly mechanically coupled to the bump pitch relaxing layer on a first side of the bump pitch relaxing layer via a first set of bump bond connections. The high-bandwidth memory component directly electrically coupled to the bump pitch relaxing layer on the first side of the bump pitch relaxing layer via the first set of bump bond connections. The bump pitch relaxing layer mechanically coupled to a first side of a substrate via second set of bump bond connections. The high-bandwidth memory component electrically coupled to the substrate via the bump-pitch relaxing layer and the second set of bump bond connections, and a bump pitch of the second set of bump bond connections is larger than the first set of bump bond connections."},"analysis":{"summary":null,"layman_explanation":null,"technical_analysis":null,"business_analysis":null,"faqs":null,"topics":[],"tech_cluster":null},"seo":{"title":"High bandwidth memory package for high performance processors","description":"Integrated component packages and methods of assembling integrated component packages are provided. The integrated component package can comprise a bump pitch relaxing layer. A high-bandwidth memory c","keywords":[]},"attribution":{"source":"Patentable","source_url":"https://patentable.app","canonical_url":"https://patentable.app/patents/US-10515920","license":"CC-BY-4.0-like","license_terms":"AI-generated analysis on this page (summary, layman_explanation, technical_analysis, business_analysis, faqs) may be reused with attribution and a visible link back to the canonical URL above. Patent abstracts, claims, and bibliographic data are USPTO public domain.","required_link":"https://patentable.app/patents/US-10515920","citation_suggestion":"Patentable. \"High bandwidth memory package for high performance processors\" (US-10515920). https://patentable.app/patents/US-10515920","copyright_holder":"Nomic Interactive Technology LLC"},"links":{"html":"https://patentable.app/patents/US-10515920","json":"https://patentable.app/api/llm-context/US-10515920","site":"https://patentable.app","llms_txt":"https://patentable.app/llms.txt"},"generated_at":"2026-05-30T11:57:57.638Z"}